Decreasing device size and increasing device density has traditionally been a high priority for the manufacturing of integrated circuits. Optical lithography has been a driving force for device scaling. Conventional optical lithography is limited to about 80 nanometer (nm) pitch for single exposure patterning. While double and other multi-patterning processes can realize smaller pitch, these approaches are expensive and more complex.
Directed self-assembly (DSA), a technique that aligns self-assembling polymeric materials on a lithographically-defined directing or guide pattern, is a potential option for extending current lithography beyond its pitch and resolution limits. The self-assembling materials, for example, are block copolymers (BCPs) that include an “A” homopolymer covalently bonded to a “B” homopolymer, which are deposited over a lithographically-defined directing pattern on a semiconductor wafer-in-process or work-in-process (WIP). The lithographically-defined directing pattern is a pre-pattern (hereinafter “DSA directing pattern”) that is encoded with spatial chemical and/or topographical information (e.g., chemical epitaxy and/or graphoepitaxy) and serves to direct the self-assembly process and the pattern formed by the self-assembling materials. Subsequently, by annealing the DSA polymers, the A polymer chains and the B polymer chains undergo micro-phase separation to form an A polymer region and a B polymer region that are registered to the underlying DSA directing pattern to define a nano-pattern (hereinafter “DSA pattern”). These A and B polymer regions are formed due to the intra- and inter-molecular forces exerted by the block copolymer macromolecules. The dimensions of these polymer regions are determined by the characteristic dimensions of the block copolymer molecules, resulting in a formation of structures with dimensions at a smaller scale compared to DSA directing patterns. Then, by removing either the A polymer block or the B polymer block by wet chemical or plasma-etch techniques, a mask is formed for transferring the DSA pattern to the underlying semiconductor WIP.
One DSA technique is graphoepitaxy in which self-assembly is directed by topographical features that are formed overlying a semiconductor WIP. This technique is used, for example, to create via and contact holes that can be subsequently filled with conductive material for forming electrical connections between one or more layers of the semiconductor WIP. In particular, the topographical features are formed overlying the semiconductor WIP using a photomask that defines mask features and conventional lithographic techniques to transfer the mask features to a photoresist layer that overlies the semiconductor WIP to form a patterned photoresist layer. The developed photoresist pattern can be used as is or further etched into underlying layers to form the topographical features that define confinement wells. By way of example, FIG. 1A illustrates a semiconductor WIP 101 that has a patterned photoresist material layer 102 formed thereover to define a plurality of confinement wells 103.
The confinement wells are filled with a BCP that is subsequently micro-phase separated to form, for example, selectively etchable cylinders or other etchable features that are each formed of either the A polymer region or the B polymer region of the BCP. The etchable cylinders are removed to form openings and define a mask for etch transferring the openings to the underlying semiconductor WIP for the formation of via and contact holes. By way of example, FIG. 1B illustrates the semiconductor WIP 101 of FIG. 1A after the confinement wells 103 have been filled with a BCP and after the BCP has micro-phase separated into a plurality of cylindrical polymer A regions 104 and polymer B regions 105 surrounding the polymer A regions 104.
In the absence of the confinement wells, cylindrical polymer regions formed in the BCP film in the manner described above typically self-assemble in hexagonally-arranged patterns, as shown in FIG. 2. Here and in the following, by a hexagon we mean a regular hexagon, that is a polygon with six vertices and six edges of equal lengths and with all internal angles equal to 120 degrees. A hexagonal overlay 200 is superimposed on the cylindrical polymer A regions 104 in FIG. 2 to better illustrate this configuration. The length of each side of the hexagonal overlay represents the natural, hexagonal separation distance between cylinders (defined from the center-point of each cylinder), which is commonly referred to in the art as separation distance L0, as illustrated. It is often the case that the layout design of the via or contact structures of an integrated circuit does not fit well with such a hexagonal configuration. Confinement wells can be used to a limited extent to form more complex shapes and displace some of the cylinders from their natural hexagonal arrangement, but this approach is limited by the resolution of the confinement well patterning process, as described above. Thus, it is not always possible to match cylinder location with the exact via/contact hole layout design of the integrated circuit. By way of example, FIG. 3 illustrates a complex-shaped confinement well 303 that has been used to attempt to match a BCP cylinder pattern with a desired layout pattern. In FIG. 3, a plurality of cylinders 312 and 313 are illustrated in the confinement well 303, and the desired layout pattern is illustrated by a plurality of via/contact structures 311 on to the confinement well 303. As shown, cylinders 312 are undesirably out of alignment from via/contacts structures 311. Moreover, cylinders 313 are formed where no via/contact structure was intended. Only at locations 314, in this example, do the cylinders and the pattern layout of via/contact structures substantially up. Thus, while confinement well 303 makes an attempt to match all cylinders with the desired pattern layout, the shortcomings of using only the confinement well to direct the cylinder placement are manifest.
Attempts have been made in the prior art to use DSA proximity correction techniques to further adjust the formation of cylinders by using various confinement well shapes to force the cylinders to deviate from their natural hexagonal arrangement. These attempts modify the formation of cylinders from their natural pattern to more closely match the desired layout design. The prior art is deficient, however, of any attempts to address the cylinder placement problem from the standpoint of the integrated circuit layout design as opposed to the confinement well design. That is, the prior has not yet sought to modify the integrated circuit layout design to better accommodate the natural (hexagonal) formation arrangement of polymeric cylinders.
Accordingly, it is desirable to provide methods for fabricating integrated circuits using DSA to form via and contact holes that more closely approximate the desired integrated circuit layout design. Additionally, it would be desirable to provide such methods that use “DSA-aware” integrated circuit layout designs to match the desired placement of via and contact holes with locations where polymeric cylinders are naturally formed (i.e., in hexagonal configurations). Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.